1. Field of the Invention
The present invention is related to the field of substrate design. In particular, the present invention is related to a method and apparatus to adaptively validate a physical net routing topology to a target topology of a substrate design.
2. Description of the Related Art
A substrate design is a physical layout of components on a circuit board and illustrates e.g., junctions, nodes, metal fills, component types and shapes, specific distances between nodes, etch endpoints, interconnects, etc. as they physically appear on the circuit board. Designers frequently use computers to design substrates from a given target topology. A physical net routing topology comprises a description of the nodes, interconnects and components of the substrate design. The physical net routing topology may be stored in a database and may be used to verify if a given target topology has been followed in the substrate design.
A target topology, typically provided by an engineer, is a logical description of the circuit that is used e.g., by a designer to design the substrate.
In order to verify that the given target topology is complied with in the substrate design, the target topology is compared with the physical net routing topology. Conventional checking algorithms that compare the given target topology with the physical net routing topology of the substrate design are inflexible and may not allow a comparison between the two topologies (i.e., the target topology and the physical net routing topology) if the two topologies differ, even though the two topologies are electrically equivalent. For example, if a test-point is added in a substrate design and the added test-point does not affect the electrical equivalence between the target topology and the physical net routing topology, conventional checking algorithms fail.